Sequential Circuits Bist with Status Bit Control

The paper proposes a Design-for-Testability (DfT) technique of Built-In Self-Test (BIST) for sequential circuits. The technique is based on making the status signals entering the control part controllable during the test mode to force the device under test to traverse all the branches in the FSM state transition graph. Extra outputs are added to the circuit under test in order to observe the values of the status bits masked out. This type of architecture requires little device area overhead since a simple controller can be implemented to manipulate the control signals. Experiments were carried out on six sequential examples in order to compare different approaches to sequential BIST. In general, the experiments show that simple LFSR does not provide an acceptable fault coverage for sequential designs. However, no universally best test generating approach was identified and the optimal solution appears to be highly dependent on design’s pseudo-random testability characteristics.